1. Field of the Invention
The present invention relates to a dynamic voltage scaling system, and in particular to a dynamic voltage scaling system having time borrowing and local boosting capability.
2. The Prior Arts
Along with the progress and development of its manufacturing process, the circuit density and performance of microprocessor have increased significantly, so that its power consumption is raised. Since battery capacity of a portable system is not sufficient to provide current for large power consumption for long period of time, so that in order to reduce power consumption, a Dynamic Voltage Scaling (DVS) technology is used extensively in digital circuit to reduce the overall power consumption. In general, in the DVS technology, the working voltage of a system can be adjusted properly according to the system requirement, so that power consumption can be reduced along with voltage reduction based on a power of 2 relations. In this respect, it is evident that DVS is capable of achieving significant reduction of power consumption.
Refer to FIGS. 1A and 1B for circuit diagrams of a circuit system designed through using a Dynamic Voltage Scaling (DVS) technology of the prior art. Also, refer to FIG. 2 for a time sequence signal waveform diagram for circuit system designed through using a Dynamic Voltage Scaling (DVS) technology of the prior art. As shown in the drawings, a flip flop 1 is connected between two adjacent logic circuits 6, and it outputs the voltage level VDD through the processing of a Critical Path Monitor (CPM) 2, a Phase Detector (PD) 3, a Voltage controller 4, and a Voltage Regulator 5. When the circuit is in operation, the clock signal clk will first pass through CPM 2. In case the time delay of signal CP passing through CPM 2 does not exceed the clock period of the system, then the system is in a safe condition, so that the system is able to further reduce the voltage level VDD produced and output by the voltage regulator 5 through the voltage controller 4, hereby further reducing power consumption. Otherwise, in case the time delay of signal CP passing through CPM 2 does exceed the clock period of the system, then the system is in an under-voltage condition, such that the circuit may operate in fault. At this time, the system may raise the voltage produced and output by the voltage regulator 5 through the voltage controller 4. In this approach, the system is able to operate stably at a lower voltage, to achieve optimization of power consumption.
In order to achieve system stability, in designing the system, the designer must make sure that the logic circuit 6 in the pipeline is operating normally and correctly. As such, in designing CPM 2, it has first to be able to detect that the CPM 2 is operating in a harmful voltage, before error does occur in operations of logic circuit 6. Therefore, in designing the CPM 2, a design margin 7 has to be reserved to make sure the logic circuit 6 operates correctly. However, considering the process variations, CPM 2 must reflect the harmful voltage before an error does occur in the logic circuit. For this reason, in designing the CPM 2, the worst process variation must be considered. In other words, more process variations have to be tolerated, such that much more design margin has to be reserved for CPM 2. In this way, the circuit can not realize effective voltage scaling, thus not being able to save power consumption efficiently.
Therefore, in order to save more power effectively, David T. Blaauw proposed a Razor-I-based Dynamic Voltage Scaling System (Razor-I DVS). Wherein, it provides a Flip Flop more tolerant of delay fault, to correct effectively delay fault of the system. Meanwhile, it monitors the error rate to adjust voltage of the voltage regulator. Yet, when the concept is proposed to reduce voltage based on the observed error rate by Razor-1, the related researches indicate that when circuit operated in this working voltage, the power saved is less than 10% of the power for error rate 0. For this reason, a Razor-II-based Dynamic Voltage Scaling System (Razor-II DVS) is subsequently proposed, to make the circuit operate near zero error rate. In this approach, circuit complexity is reduced significantly to lower power consumption. Meanwhile, local data recovery of the system is avoided, to reduce system design complexity significantly, in achieving the same effect of system voltage reduction as in Razor-I.
However, it is worth to note that, regardless of Razor-I or Razor-II, when system error occurs, Data Recovery or Instruction Replay must be performed, to bring the system back to normal operation, such that this approach of solving system error requires an additional cycle period or tens of cycle periods. When this happens to a large system work load, it could greatly reduce system data throughput, to affect seriously performance of the system.
Therefore, presently, the design and performance of the dynamic voltage scaling system is not quite satisfactory, and it has much room for improvements.